1. Field of the Invention
This invention relates to a solid state image sensing device and a method of manufacturing the device, and more particularly, to a highly integrated solid state image sensing device and a method of making such a device.
2. Description of the Related Art
A plan view of a part of a prior art solid state image sensing device is shown in FIG. 1, wherein reference numeral 1 is a first transfer electrode and 2 a second transfer electrode, which generally have a two layer structure of polysilicon layers, which in FIG. 1 are shown in the form of a single layer for the sake of brevity. The hatched areas 3 indicate isolation regions, 4 indicates a photoelectric conversion element and 5 indicates a charge transfer channel region. As an aid in understanding the structure, a cross section of
the device taken along the line XII--XII of FIG. 1 is shown in FIG. 2. Each channel region 5 is generally formed of an N-type impurity layer and serves as a buried channel known in the art. The photoelectric conversion element 4 is in the form of a buried region formed by covering the surface of an N.sup.+ type impurity layer 7 with a P.sup.+ type impurity region 6. This arrangement permits the surface region of the N.sup.+ type impurity layer 7 to be maintained in a non-depleted state to render inactive carriers that are present in the interface. The significance of this is that the leak current is greatly decreased.
The isolation region 3 is formed of a P.sup.+ type impurity layer and electrically isolates the layer 7 from the layer 5 lying at one side thereof. No isolation layer 3 is formed, but a charge readout channel 15 is formed, between each layer 7 and layer 5 lying at the opposite side thereof. The charge readout channel 15 is controlled by the voltage of the electrode 2 and transfers signal charges (electrons) from the layer 7 to the layer 5.
Reference numeral 8 indicates an N type substrate, 9 a P type well layer, 10 light shield films for preventing image light from being incident to the charge transfer devices, and 11 an insulating film.
In the conventional structure, to ensure that the P.sup.+ layer 3 is positively overlapped with an end of each electrode 2, even when a masking deviation occurs in the manufacturing steps, an allowance of 0.5-1.0 .mu.m in the lateral direction of the layer 3 is provided for compensating the deviation. Thus, the P.sup.+ layer 3 is formed prior to the formation of each electrode 2. Device performance, on the other hand, is determined by the abilities of the photoelectric conversion elements and the charge transfer devices, and is enhanced virtually in proportion to their areas lying in the horizontal plane. That is, the area of the P.sup.+ layer 7 needs to be increased to attain high sensitivity, and the N layer 5 needs to be broadened to implement a wide dynamic range (a large maximum amount of signal charge). It therefore is required that the isolation layer 3 be formed as narrow as possible in width. In forming the isolation layer 3, a P type impurity is implanted into a substrate by lithographic techniques using a resist pattern patterned to the most possible minimum size. The implanted impurity, however, is thermally diffused in a subsequent thermal step to cause the isolation layers 3 to occupy broad regions. For example, the P type layer formed with 1.0 .mu.m width by use of a resist pattern of a 1.0 .mu.m size is expanded for example to a 2.0 .mu.m width after the heating step. The structure shown in FIGS. 1 and 2 requires the formation of P.sup.+ layers 3 at both sides of the photoelectric conversion element. If the above method is applied to the structure of FIG. 2, the width of the isolation layer 3 formed after the thermal step by a lithographic technique of a minimum width of 1.0 .mu.m results in 2 .mu.m required at each side of the conversion element and hence totally equals 4 .mu.m. This is obviously against the goal of achieving high integration (a number of pixels) in the fabrication of solid state image sensors.